In semiconductor technology, an integrated circuit pattern can be defined on a substrate using a photolithography process. A damascene or a dual damascene process is utilized to form multilayer copper interconnections including vertical interconnection vias/contacts and horizontal interconnection metal lines. During a damascene process, a plug filling material is employed to fill in the vias (or contacts) and the material is then polished back. However, as semiconductor technologies move forward to advanced technology nodes with smaller feature sizes, such as 20 nm, 16 nm or less, a variety of issues with less tolerance may arise such as misalignments, damage to already formed conductive feature, etc.
Therefore, the present disclosure provides an interconnection structure and a method of making the same to address the above issues.